FIG. 1 schematically illustrates the architecture of a conventional LCD panel. As shown in FIG. 1, the LCD panel comprises a gate driver 120, a source driver 110, and a thin film transistor array (TFT array) 100. The TFT array 100 comprises a plurality of pixel units P11˜Pnn. The gate driver 120 is connected to a plurality of gate lines (not shown) of the TFT array 100. In addition, a plurality of gate pulses generated by the gate driver 120 are sequentially transmitted to the gate lines from top to bottom. In response to each gate pulse, a corresponding row of pixel units are turned on. Moreover, in response to each gate pulse, a plurality of source signals are generated by the source driver 110 according to an image signal (Data). Through a plurality of source lines of the TFT array 100, these source signals are transmitted to the pixel units which are turned on.
FIG. 2 is a schematic circuit block diagram illustrating the source driver of the conventional LCD panel. After the digital image signal (Data) is inputted into the source driver 110, the logic level of the image signal (Data) is changed by a level shifter 112. The image signal (Data) with the changed logic level is inputted into a digital-to-analog converter (DAC) 114. The digital-to-analog converter 114 issues a plurality of input signals to an output buffering unit 116. In response to the input signals, a plurality of source signals O1˜On are generated by the output buffering unit 116 and transmitted to a plurality of source lines.
In the TFT array 100 of a specified LCD panel (e.g. a dot inversion LCD panel), the polarities of every two adjacent ones of the source signals O1˜On should be opposite because of the unique configuration of the pixel units. In addition, the polarities of any source signal and a successive source signal which are transmitted to the same source line are also opposite. For example, in response to a first gate pulse, the source signals O1˜On on the source lines have polarities (+,−,+,−, . . . +,−). In response to a second gate pulse, the source signals O1˜On on the source lines have polarities (−,+,−,+, . . . −,+). In response to a third gate pulse, the source signals O1˜On on the source lines have polarities (+,−,+,−, . . . +,−). The rest may be deduced by analogy.
Please refer to FIG. 2 again. The output buffering unit 116 comprises plural positive and negative voltage input operational amplifier sets 116a˜116z. Each of the positive and negative voltage input operational amplifier sets 116a˜116z issues two source signals with opposite polarities to the two adjacent source lines.
FIG. 3 is a schematic circuit diagram illustrating a conventional positive and negative voltage input operational amplifier set. As shown in FIG. 3, the positive and negative voltage input operational amplifier set 116a comprises a positive operational amplifier POP, a negative operational amplifier NOP, and a switching unit SW. The positive operational amplifier POP and the negative operational amplifier NOP are both rail-to-rail input operational amplifiers. That is, the voltages of the input signal and the output signals of the positive operational amplifier POP are both in the range between the voltage of the positive voltage source PAVDD and the voltage of a ground voltage source GND, and the voltages of the input signal and the output signals of the negative operational amplifier NOP are both in the range between the voltage of the ground voltage source GND and the voltage of a negative voltage source NAVDD.
The two power terminals of the positive operational amplifier POP are connected to the positive voltage source PAVDD and the ground voltage source GND, respectively. A first input signal IN1 is inputted into a positive input terminal of the positive operational amplifier POP. An output signal (a first output signal OUT1) of the positive operational amplifier POP is fed back to a negative input terminal of the positive operational amplifier POP. Consequently, the first output signal OUT1 is equal to the first input signal IN1. In addition, the input voltage of the first input signal IN1 is limited to be in the range between the voltage of the positive voltage source PAVDD and the voltage of a ground voltage source GND.
The two power terminals of the negative operational amplifier NOP are connected to the ground voltage source GND and the negative voltage source NAVDD, respectively. A second input signal IN2 is inputted into a positive input terminal of the negative operational amplifier NOP. An output signal (a second output signal OUT2) of the negative operational amplifier NOP is fed back to a negative input terminal of the negative operational amplifier NOP. Consequently, the second output signal OUT2 is equal to the second input signal IN2. In addition, the input voltage of the second input signal IN2 is limited to be in the range between the voltage of the ground voltage source GND and the voltage of a negative voltage source NAVDD.
The switching unit SW may be operated in two statuses. In a case that the switching unit SW is operated in the first status, by the switching unit SW, the first output signal OUT1 is switched to a positive-polarity first source signal O1 and the second output signal OUT2 is switched to a negative-polarity second source signal O2. In a case that the switching unit SW is operated in the second status, by the switching unit SW, the first output signal OUT1 is switched to a positive-polarity second source signal O2 and the second output signal OUT2 is switched to a negative-polarity first source signal O1. That is, when the switching unit SW is operated between the two statuses, the polarities of every two adjacent ones of the source signals O1˜On are opposite. In addition, the polarities of any source signal and a successive source signal which are transmitted to the same source line are also opposite.
FIGS. 4A and 4B are schematic circuit diagrams respectively illustrating the positive operational amplifier and the negative operational amplifier of the conventional positive and negative voltage input operational amplifier set.
As shown in FIG. 4A, the positive operational amplifier POP comprises a first differential pair including a first PMOS transistor MP1 and a second PMOS transistor MP2, a first current source I1, a first active region controlling circuit 402, a second differential pair including a first NMOS transistor MN1 and a second NMOS transistor MN2, a second current source I2, a second active region controlling circuit 404, and an output stage circuit 406.
The gate terminal of the first PMOS transistor MP1 is the positive input terminal (+) of the positive operational amplifier POP for receiving the first input signal IN1. The gate terminal of the second PMOS transistor MP2 is the negative input terminal (−) of the positive operational amplifier POP. The first current source I1 is connected between the source terminal of the first PMOS transistor MP1 and the positive voltage source PAVDD. In addition, the source terminal of the first PMOS transistor MP1 and the source terminal of the second PMOS transistor MP2 are connected with each other. A first terminal of the first active region controlling circuit 402 is connected to the drain terminal of the first PMOS transistor MP1. A second terminal of the first active region controlling circuit 402 is connected to the drain terminal of the second PMOS transistor MP2. A third end of the first active region controlling circuit 402 is connected to the ground voltage source GND. The first current source I1 and the first active region controlling circuit 402 are used for controlling the first PMOS transistor MP1 and the second PMOS transistor MP2 to be operated at the active region.
The gate terminal of the first NMOS transistor MN1 is connected to the gate terminal of the first PMOS transistor MP1. The gate terminal of the second NMOS transistor MN2 is connected to the gate terminal of the second PMOS transistor MP2. The second current source I2 is connected between the source terminal of the first NMOS transistor MN1 and the ground voltage source GND. In addition, the source terminal of the first NMOS transistor MN1 and the source terminal of the second NMOS transistor MN2 are connected with each other. A first terminal of the second active region controlling circuit 404 is connected to the drain terminal of the first NMOS transistor MN1. A second terminal of the second active region controlling circuit 404 is connected to the drain terminal of the second NMOS transistor MN2. A third end of the second active region controlling circuit 404 is connected to the positive voltage source PAVDD. The second current source I2 and the second active region controlling circuit 404 are used for controlling the first NMOS transistor MN1 and the second NMOS transistor MN2 to be operated at the active region.
The two power terminals of the output stage circuit 406 are connected between the positive voltage source PAVDD and the ground voltage source GND. A first terminal of the output stage circuit 406 is connected to the drain terminal of the second NMOS transistor MN2. A second terminal of the output stage circuit 406 is connected to the drain terminal of the first PMOS transistor MP1. The output terminal of the output stage circuit 406 is connected to the gate terminal of the second PMOS transistor MP2 for generating the first output signal OUT1.
Expect for the following items, the configurations of the negative operational amplifier NOP of FIG. 4B are similar to those of the positive operational amplifier POP of FIG. 4A. For example, the second input signal IN2 is received by the positive terminal (+) of the negative operational amplifier NOP, the output terminal of the output stage circuit 406 generates the second output signal OUT2, and the two power terminals of the output stage circuit 406 are respectively connected to the ground voltage source GND and the negative voltage source NAVDD.
As described in FIGS. 4A and 4B, an operational amplifier has two differential pairs for achieving the function of rail-to-rail. In addition, a current source and an active region controlling circuit are needed for controlling a corresponding differential pair to be operated at the active region. In other words, the conventional positive and negative voltage input operational amplifier set needs four differential pairs, four current sources, and four active region controlling circuits totally. Under this circumstance, the layout area is increased, the static current is too high, and the power consumption is increased.